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ltc6605-14 1 660514f typical application features applications description dual matched 14mhz filter with low noise, low distortion differential ampli er the ltc ? 6605-14 contains two independent, fully differ- ential ampli? ers con? gured as matched 2nd order 14mhz lowpass ? lters. the f C3db of the ? lters is adjustable in the range of 12.4mhz to 20mhz and 25mhz. the internal op amps are fully differential, feature very low noise and distortion, and are compatible with 16-bit dynamic range systems. the inputs can accept single- ended or differential signals. an input pin is provided for each ampli? er to set the common mode level of the differential outputs. internal laser-trimmed resistors and capacitors determine a precise, very well matched (in gain and phase) 14mhz 2nd order ? lter response. a single optional external re- sistor per channel can tailor the frequency response for each ampli? er. three-state bias pins determine each ampli? ers power consumption, allowing a choice between shutdown, me- dium power or full power. the ltc6605-14 is available in a compact 6mm 3mm 22-pin leadless dfn package and operates over a C40c to 85c temperature range. dual, matched 12.4mhz lowpass filter n two matched 14mhz 2nd order lowpass filters with differential ampli? ers gain match: 0.25db max, passband phase match: 1.1 max, passband single-ended or differential inputs n < C84dbc distortion in passband n 2.1nv/ hz op amp noise density n pin-selectable gain (0db/6db/9.5db) n pin-selectable power consumption (0.35ma/ 16.2ma/33.1ma) n rail-to-rail output swing adjustable output common mode voltage control buffered, low impedance outputs n 2.7v to 5.25v supply voltage n small 22-pin 6mm 3mm 0.75mm dfn package n broadband wireless adc driver/filter n antialiasing filter n single-ended to differential conversion n dac smoothing filter n zero-if direct conversion receivers , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. channel to channel phase matching phase match (deg) number of units 0 20 160120 140 60 C1.0 0 0.6 0.2 1.0 66057 ta01b 80 100 40 C0.2 C0.6 354 typical units t a = 25 f in = 14mhz 660514 ta01 ltc6605-14 3v 0.1f 0.1f 0.1f 0.1f C + 21 19 17 v outa + C 22 18 3v C + 15 14 13 16 12 2 3 4 6 v outb + C 1 5 8 9 10 7 11 20 v ina 3v 3v +C v inb +C downloaded from: http:///
ltc6605-14 2 660514f dc electrical characteristics pin configuration absolute maximum ratings total supply voltage (v + to v C ) ................................5.5v input current (note 2) ..........................................10ma output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4).... C40c to 85c speci? ed temperature range (note 5) .... C40c to 85c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c (note 1) 2221 20 19 18 17 16 15 14 13 12 12 3 4 5 6 7 8 9 1011 Cout av + a v C v ocma +out av C Cout bv + b v C v ocmb +out b +in2 a+in1 a bias a Cin1 aCin2 a v C +in2 b+in1 b bias b Cin1 bCin2 b top view 23 djc package 22-lead (6mm 3mm) plastic dfn t jmax = 150c, ja = 46.5c/w exposed pad (pin 23) is v C , must be soldered to pcb order information lead free finish tape and reel part marking* package description temp erature range ltc6605cdjc-14#pbf ltc6605cdjc-14#trpbf 660514 22-lead (6mm 3mm) plastic dfn 0c to 70c ltc6605idjc-14#pbf ltc6605idjc-14#trpbf 660514 22-lead (6mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temp erature ranges. *the temperature grade is identi? ed by a l abel on the shipping container. consult ltc marketing for information on non-standard lead based ? ni sh parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v os differential offset voltage (at op amp inputs) (note 6) v s = 2.7v to 5v l 0.25 1 mv v os / t differential offset voltage drift (at op amp inputs) bias = v + bias = floating ll 11 v/c v/c i b input bias current (at op amp inputs) (note 7) bias = v + bias = floating ll C60 C30 C25 C12.5 00 aa i os input offset current (at op amp inputs) (note 7) 1 a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, bias tied to v + , r l = open, r bal = 10k. the ? lter is con? gured for a gain of 1, unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v incm is de? ned as (v inp + v inm )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ). see figure 1. downloaded from: http:///
ltc6605-14 3 660514f symbol parameter conditions min typ max units v incm input common mode voltage range (note 8) v s = 3v v s = 5v ll C0.2 C0.2 1.7 4.7 vv cmrr common mode rejection ratio ( v incm / v os ) (note 9) v s = 3v; v incm = 1.5v v s = 5v; v incm = 2.5v ll 4646 7474 dbdb psrr power supply rejection ratio ( v s / v os ) (note 10) v s = 2.7v to 5v l 66 95 db v oscm common mode offset voltage (v outcm C v ocm ) v s = 3v v s = 5v ll 10 10 15 15 mvmv v ocm output common mode range (valid range for v ocm pin) (note 8) v s = 3v v s = 5v ll 1.1 1.1 24 vv v mid self-biased voltage at the v ocm pin v s = 3v l 1.475 1.5 1.525 v r vocm input resistance of v ocm pin l 12.5 18.8 23.5 k v out output voltage swing, high (measured relative to v + ) v s = 3v; i l = 0ma v s = 3v; i l = 5ma v s = 3v; i l = 20ma ll l 245 285 415 450 525 750 mvmv mv v s = 5v; i l = 0ma v s = 5v; i l = 5ma v s = 5v; i l = 20ma ll l 350 390 550 625 700 1000 mvmv mv output voltage swing, low (measured relative to v C ) v s = 3v; i l = 0ma v s = 3v; i l = C5ma v s = 3v; i l = C20ma ll l 120 135 195 225 250 350 mvmv mv v s = 5v; i l = 0ma v s = 5v; i l = C5ma v s = 5v; i l = C20ma ll l 175 200 270 325 360 475 mvmv mv i sc output short-circuit current (note 3) v s = 3v v s = 5v ll 40 50 70 95 mama v s supply voltage l 2.7 5.25 v i s supply current (per channel) v s = 2.7v to 5v; bias = v + v s = 2.7v to 5v; bias = floating v s = 2.7v to 5v; bias = v C ll l 33.1 16.2 0.35 45 26.5 1.6 mama ma bias pin range for shutdown referenced to v C l 00 . 4 v bias pin range for medium power referenced to v C l 11 . 5 v bias pin range for full power referenced to v C l 2.3 v s v bias pin self-biased voltage (floating) referenced to v C l 1.05 1.15 1.25 v r bias bias pin input resistance l 100 150 200 k t on turn-on time v s = 3v, v bias = v C to v + 400 ns t off turn-of f time v s = 3v, v bias = v + to v C 400 ns dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, bias tied to v + , r l = open, r bal = 10k. the ? lter is con? gured for a gain of 1, unless otherwise noted . v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v incm is de? ned as (v inp + v inm )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ). see figure 1. downloaded from: http:///
ltc6605-14 4 660514f ac electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v incm = v ocm = mid-supply, v bias = v + , unless otherwise noted. filter con? gured as in figure 2, unless otherwi se noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v incm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v +in + v Cin ). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all pins are protected by steering diodes to either supply. if any pin is driven beyond the ltc6605-14s supply voltage, the excess input current (current in excess of what it takes to drive that pin to the sup ply rail) should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. long-term application of output currents in excess o f the absolute maximum ratings may impair the life of the device. note 4: both the ltc6605c and the ltc6605i are guaranteed functional over the operating temperature range C40c to 85c. note 5: the ltc6605c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6605c is designed, characterized and expected to meet speci? ed performance from C40c to 85c, but is not tested or qa sampled at these temperatures. the ltc6605i is guaranteed to meet speci? ed performance from C40c to 85c. note 6: output referred voltage offset is a function of gain. to determine output referred voltage offset, or output voltage offset drift, multiply v os by the noise gain (1 + gain). see figure 3. note 7: input bias current is de? ned as the average of the currents ? owing into the noninverting and inverting inputs of the internal ampli? er and is calculated from measurements made at the pins of the ic. input offset current is de? ned as the difference of the currents ? owing into the noninverting and inverting inputs of the internal ampli? er and is calculated from measurements made at the pins of the ic. symbol parameter conditions min typ max units gain filter gain v in = 0.125v, dc v indiff = 0.5v p-p , f = 7mhz v indiff = 0.5v p-p , f = 10.5mhz v indiff = 0.5v p-p , f = 14mhz v indiff = 0.5v p-p , f = 28mhz v indiff = 0.5v p-p , f = 70mhz ll l l l l C0.25 C1.25 C2.5 C4.15 C11.65 C28 0.05 C0.92 C2.12 C3.75 C11.1 C25.2 0.25 C0.6 C1.75 C3.35 C10.6 C24.3 dbdb db db db db phase filter phase v in = 0.125v, dc v indiff = 0.5v p-p , f = 7mhz v indiff = 0.5v p-p , f = 10.5mhz v indiff = 0.5v p-p , f = 14mhz 0 C43.3 C63.6 C81.2 degdeg deg deg gain gain match (channel-to-channel) v in = 0.125v, dc v indiff = 0.5v p-p , f = 7mhz v indiff = 0.5v p-p , f = 10.5mhz v indiff = 0.5v p-p , f = 14mhz ll l l C0.175 C0.2 C0.2 C0.25 0.04 0.04 0.04 0.05 0.175 0.2 0.2 0.25 dbdb db db phase phase match (channel-to-channel) v indiff = 0.5v p-p , f = 7mhz v indiff = 0.5v p-p , f = 10.5mhz v indiff = 0.5v p-p , f = 14mhz ll l C0.9 C1.0 C1.1 0.2 0.2 0.2 0.9 1.0 1.1 degdeg deg 2v/v gain filter gain in 2v/v con? guration inputs at in1 pins, in2 pins floating v in = 0.125v, dc l 5.8 6 6.25 db channel separation v indiff = 1v p-p , f = 7mhz C96 db f o tc filter cut-off frequency temperature coef? cient (t = C45c to 85c) bias = v + bias = floating C95 C230 ppm/c ppm/c noise integrated output noise (bw = 10khz to 28mhz) 54 v rms input referred noise density (f = 1mhz) bias = v + figure 4, gain = 1 figure 4, gain = 2 figure 4, gain = 3 13.2 6.6 4.4 nv/ hz nv/ hz nv/ hz e n voltage noise density referred to op amp inputs (f = 1mhz) bias = v + bias = floating 2.1 2.6 nv/ hz nv/ hz i n current noise density referred to op amp inputs (f = 1mhz) bias = v + bias = floating 3 2.1 pa/ hz pa/ hz hd2 2nd harmonic distortion f in = 7mhz; v in = 2v p-p single-ended bias = v + bias = floating, r load = 400 C81 C69 dbc dbc hd3 3rd harmonic distortion f in = 7mhz; v in = 2v p-p single-ended bias = v + bias = floating, r load = 400 C93 C76 dbc dbc downloaded from: http:///
ltc6605-14 5 660514f electrical characteristics supply current vs temperature filter gain vs temperature C3db frequency vs temperature filter frequency response typical performance characteristics note 8: see the applications information section for a detailed discussion of input and output common mode range. input common mode range is tested by measuring the differential dc gain with v incm = mid-supply, and again with v incm at the input common mode range limits listed in the electrical characteristics table, with v in = 0.25, verifying that the differential gain has not deviated from the mid-su pply common mode input case by more than 0.5%, and that the common mode offset (v oscm ) has not deviated from the mid-supply common mode offset by more than 10mv. output common mode range is tested by measuring the differentia l dc gain with v ocm = mid-supply, and again with voltage set on the v ocm pin at the output common range limits listed in the electrical characteris tics table, verifying that the differential gain has not deviated from the mid-supply common mode input case by more than 0.5%, and that the common mode offset (v oscm ) has not deviated by more than 10mv from the mid-supply case. note 9: cmrr is de? ned as the ratio of the change in the input common mode voltage at the internal ampli? er inputs to the change in differenti al input referred voltage offset (v os ). note 10: power supply rejection ratio (psrr) is de? ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset (v os ). temperature (c) C60 15.012.5 supply current (ma) 17.5 22.5 25.0 27.5 32.5 C20 20 40 660514 g01 20.0 35.0 37.5 30.0 C40 0 60 80 100 v s = 2.7v, bias = float v s = 3v, bias = float v s = 5v, bias = float v s = 2.7v, bias = v + v s = 3v, bias = v + v s = 5v, bias = v + v incm = v ocm = mid-supply temperature (c) C60 0.990 gain (v/v) 0.995 1.005 1.010 C20 20 40 660514 g02 1.000 C40 0 60 80 100 v s = 3v, bias = v + v incm = v ocm = mid-supply 5 representative units temperature (c) C60 C2.0 frequency shift of f C3db (%) C1.0C1.5 0 2.01.5 1.0 0.5 C20 20 40 660514 g03 C0.5 C40 0 60 80 100 bias = floatbias = v + v s = 3v v incm = v ocm = 1.5v frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 10 10 1.0 100 1000 660514 g04 v s = 3v v incm = v ocm = mid supply bias = v + bias pin floating downloaded from: http:///
ltc6605-14 6 660514f typical performance characteristics harmonic distortion vs input amplitude harmonic distortion vs input common mode voltage (v s = 5v) differential output noise vs frequency harmonic distortion vs frequency, bias high harmonic distortion vs frequency, bias floating channel separation vs frequency overdrive transient respon se harmonic distortion vs input common mode voltage (v s = 3v) frequency (mhz) 0.1 distortion (dbc) C40C50 C60 C70 C80 C90 C100C110 C120 1 10 100 660514 g05 v in = 2v p-p ,v s = 3v r l = 400 differential, gain = 1v/v differential input, hd2differential input, hd3 single-ended input, hd2 single-ended input, hd3 frequency (mhz) 0.1 distortion (dbc) C40C50 C60 C70 C80 C90 C100C110 C120 1 10 100 660514 g06 v in = 2v p-p ,v s = 3v r l = 400 differential, gain = 1v/v differential input, hd2differential input, hd3 single-ended input, hd2 single-ended input, hd3 v s = 3v, bias tied to v + ,v incm = v ocm = 1.5v, r load = 400, f in = 3mhz, gain = 1v/v v in (v p-p ) 0 C120 distortion (dbc) C110 C90 C80 C70 C50 2 4 5 660514 g07 C100 C40 C60 13 6 differential input, hd2differential input, hd3 single-ended input, hd2 single-ended input, hd3 v in = 2v p-p ,v ocm = 1.5v bias = 3v, f = 3mhzr l = 400 differential, gain = 1v/v input common mode voltage (v) C0.5 C120 distortion (dbc) C110 C90 C80 C70 C50 0.5 1.5 2 2.5 660514 g08 C100 C40 C60 01 3 differential input, hd2differential input, hd3 single-ended input, hd2 single-ended input, hd3 v in = 2v p-p ,v ocm = 2.5v bias = 5v, f = 3mhzr l = 400 differential, gain = 1v/v input common mode voltage (v) 0 C0.5 C120 distortion (dbc) C110 C90 C80 C70 C50 1.5 1 3.5 3 4.5 5 4 660514 g09 C100 C40 C60 0.5 2.5 2 differentialinput, hd2 differential input, hd3 single-ended input, hd2 single-ended input, hd3 frequency (mhz) 10 noise spectral density (nv/ hz ) integrated noise (v rms ) 100 0.001 0.1 1 100 10 660514 g10 1 0.01 1 10 1000.1 1000 output noise spectral density integrated output noise v s = 3v bias tied to v + frequency (mhz) channel separation (db) 0.1 10 100 1000 660514 g11 C120 1 C20C30 C40 C50 C60 C70 C80 C90 C100C110 bias = v + bias = float v in = 1v p-p ,v s = 3v r l = 400 differential 50ns/div voltage (v) 660514 g12 2.01.5 1.0 0.5 0 C0.5C1.0 C1.5 C2.0 v s = 3v, v ocm = 1.5v bias = 3v, r load = 400 +outCout Cin2 +in2 downloaded from: http:///
ltc6605-14 7 660514f test circuits 660514 tc02 200 81.5pf 21 19 22 18 2 3 4 1 5 20 48.2pf 100 200125 50 0.1f 100 100 200 48.2pf v + v C 81.5pf 100 36k36k 200 125 bias bias v + v ocm coilcraft ttwb-4-b 0.1f 0.01f 0.1f v C 1f v in + C 1f 1f 1f ltc6605-14 C + C + v +out v Cout v +in v Cin 660514 tc01 200 ltc6605-14 81.5pf 21 19 22 18 2 3 4 1 5 20 48.2pf 100 200125 0.1f 25 25 200 48.2pf v + v C 81.5pf 100 36k36k 200 125 C + C + bias bias v + v Cout v +out v ocm i l v outcm r bal v inp r bal 0.1f 0.01f 0.1f v C + C v inm + C i l figure 1. dc test circuit (channel a shown) figure 2. ac test circuit (channel a shown) downloaded from: http:///
ltc6605-14 8 660514f pin functions +in2 a, Cin2 a, +in2 b, Cin2 b (pins 1, 5, 7, 11): inputs to trimmed 200 resistors. can accept an input signal, be ? oated, tied to an output pin, or connected to external components. +in1 a, Cin1 a, +in1 b, Cin1 b (pins 2, 4, 8, 10): inputs to trimmed 100 resistors. can accept an input signal, be ? oated, tied to an output pin, or connected to external components. bias a, bias b (pins 3, 9): three-state input to select ampli? er power consumption. drive low for shutdown, drive high for full power, leave ? oating for medium power. bias presents an input resistance of approximately 150k to a voltage 1.15v above v C . v C (pins 6, 14, 17, 20): negative supply. all v C pins should be connected to the same voltage, either a ground plane or a negative supply rail. v ocma , v ocmb (pins 19, 13): the voltage applied to these pins sets the output common mode voltage of each ? lter channel. if left ? oating, v ocm self-biases to a voltage midway between v + and v C . v + a, v + b (pins 21, 15): positive supply for filter channel a and b, respectively. these are not connected to each other internally. Cout a, +out a, Cout b, +out b (pins 22, 18, 16, 12): differential output pins. exposed pad (pin 23): always tie the underlying exposed pad to v C . if split supplies are used, do not tie the pad to ground. downloaded from: http:///
ltc6605-14 9 660514f block diagram +in2 a+in1 a bias a Cin1 aCin2 a Cout av + a v C v ocma +out a +in2 b+in1 b bias b Cin1 bCin2 b Cout bv + b v ocmb +out b 660514 bd 200 81.5pf 21 19 17 22 18 15 14 13 16 12 2 3 4 1 5 8 9 10 7 6 11 20 48.2pf 100 200125 200 48.2pf v C v + a 81.5pf 100 36k36k 200 125 C + C + bias 200 81.5pf 48.2pf 100 200125 200 48.2pf v C v + b 81.5pf 100 36k36k 200 125 C + C + bias v C v C v C downloaded from: http:///
ltc6605-14 10 660514f functional description the ltc6605-14 is designed to make the implementation of high frequency fully differential ? ltering functions very easy. two very low noise ampli? ers are surrounded by precision matched resistors and precision matched capaci- tors enabling various ? lter functions to be implemented by hard wiring pins. the ampli? ers are wide band, low noise and low distortion fully differential ampli? ers with accurate output phase balancing. they are optimized for driving low voltage, single-supply, differential input analog-to- digital converters (adcs). the ltc6605-14 operates with a supply voltage as low as 2.7v and accepts inputs up to 325mv below the v C power rail, which makes it ideal for converting ground referenced, single-ended signals into differential signals that are referenced to the user-supplied common mode voltage. this is ideal for driving low volt- age, single-supply, differential input adcs. the balanced differential nature of the ampli? er and matched surround- ing components provide even-order harmonic distortion cancellation, and low susceptibility to common mode noise (like power supply noise). the ltc6605-14 can be operated with a single-ended input and differential output, or with a differential input and differential output. the outputs of the ltc6605-14 can swing rail-to-rail. they can source or sink a transient 70ma of current. load capacitances should be decoupled with at least 25 of series resistance from each output. filter frequency response and gain adjustment figure 3 shows the ? lter architecture. the laplace transfer function can be expressed in the form of the following generalized equation for a 2nd order lowpass ? lter: v out(diff) v in(diff) = gain 1 + s 2 f o ?q + s 2 2 f o () 2 , with gain, f o and q as given in figure 3. note that gain and q of the ? lter are based on component ratios, which both match and track extremely well over temperature. the corner frequency f o of the ? lter is a function of an rc product. this rc product is trimmed to 1% and is not expected to drift by more than 1% from nominal over the entire temperature range C40c to 85c. as a result, fully differential ? lters with tight magnitude, phase tolerance and repeatability are achieved. various values for resistors r1 and r4 can be formed by pin-strapping the internal 100 and 200 resis- tors, and optionally by including one or more external resistors. note that non-zero source resistance should be combined with, and included in, r1. figure 3. filter architecture and equations applications information C + + C v out(diff) 660514 f03 v in(diff) r2 200 r2 200 r3 125 r3 125 r1r1 r4 = r4a + r4b + r ext r ext r4a r4b c148.2pf c148.2pf c2 81.5pf c281.5pf C + C + downloaded from: http:///
ltc6605-14 11 660514f applications information setting the passband gain (gain = r2/r1) only requires choosing a value for r1, since r2 is a ? xed internal 200. therefore, the following three gains can be easily con? gured without external components: table 1. con? guring the passband gain without external components gain (v/v) gain (db) r1 () input pins to use 1 0 200 drive the 200 resistors. tie the 100 resisters together. 2 6 100 drive the 100 resistors. 3 9.5 66.7 drive the 200 and 100 resistors in parallel. the resonant frequency, f o , is independent of r1, and therefore independent of the gain. for any ltc6605-14 ? lter con? guration that conforms to figure 3, the f o is ? xed at 16.1mhz. the f C3db frequency depends on the combina- tion of f o and q. for any speci? c gain, q is adjusted by the selection of r4.setting the f C3db frequency using an external resistor (r ext ), the f C3db frequency is ad- justable in the range of 12.4mhz to 20.0mhz (see figure 3). the minimum f C3db is set for r ext equal to 0 and the maximum f C3db is arbitrarily set for a maximum passband gain peak less than 1db. table 2. r ext selection gain = 1, r1 = 200, r4a = r4b = 100 f C3db (mhz) r ext 12.4 0 14 30.9 14.5 41.2 15 52.3 15.5 64.9 16 78.7 16.5 80.6 17 110 17.5 127 18 150 18.5 174 19 205 19.5 241 20 287 figure 4 shows three filter configurations with an f C3db = 12.3mhz, without any external components. these ? lters have a q = 0.57, which is an almost ideal bessel characteristic with linear phase. figure 5 shows ? lter con? gurations that use some external resistors, and are tailored for a very ? at passband. many other con? gurations are possible by using the equa- tions in figure 3. for example, external resistors can be added to modify the value of r1 to con? gure gain 1. for an even more ? exible ? lter ic with similar performance, consider the ltc6601. bias pin each channel of the ltc6605-14 has a bias pin whose function is to tailor both performance and power. the bias pin can be modeled as a voltage source whose potential is 1.15v above the v C supply and that has a thevenin equivalent resistance of 150k. this three-state pin has ? xed logic levels relative to v C (see the electrical characteristics table), and can be driven by any external source that can drive the bias pins equivalent input impedance. if the bias pin is tied to the positive supply, the part is in a fully active state con? gured for highest performance (lowest noise and lowest distortion). if the bias pin is ? oated (left unconnected), the part is in a fully active state, but with ampli? er currents reduced and performance scaled back to preserve power consumption. care should be taken to limit external leakage currents to this pin to under 1a to avoid putting the part in an unexpected state. if the bias pin is tied to the most negative supply (v C ), the part is in a low power shutdown mode with ampli? er outputs disabled. in shutdown, all internal biasing current sources are shut off, and the output pins each appear as open collectors with a non-linear capacitor in parallel and steering diodes to either supply. because of the non-linear capacitance, the outputs can still sink and source small amounts of transient current if exposed to signi? cant voltage transients. using this function to wire-or outputs together is not recommended. downloaded from: http:///
ltc6605-14 12 660514f frequency (mhz) 0.1 phase (deg) group delay (ns) C100 C120 C140 C160 C180 C200 02 0 1816 14 12 10 8 6 4 2 0 C20C40 C60 C80 10 1 100 1000 660514 g04i phase group delay figure 4. f C3db = 12.3mhz filter con? gurations without external components applications information gain response gain response gain response phase and group delay response small signal step response 660514 f04c f C3db = 12.3mhz gain = 3v/ v (9.5db) z in = 133 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 660514 f04a f C3db = 12.3mhz gain = 1v/ v (0db) z in = 400 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 660514 f04b f C3db = 12.3mhz gain = 2v/ v (6db) z in = 200 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 2010 10 1 100 1000 660514 g04d frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 2010 10 1 100 1000 660514 g04e frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 2010 10 1 100 1000 660514 g04f 100mv/div 660514 g04j 20ns/div gain = 1v/ v downloaded from: http:///
ltc6605-14 13 660514f applications information 660514 f05a C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 0.4db 14mhz passband gain = 1v/ v (0db) z in = 400 200200 660514 f05c 0.4db 14mhz passband gain = 2v/ v (6db) z in = 200 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 figure 5. flat passband filter con? gurations with some exte rnal resistors gain response gain response passband phase and group delay small signal step response frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 10 10 1 100 1000 660514 g05e frequency (mhz) 0.1 C40 gain magnitude (db) C30 C20 C10 0 10 10 1 100 1000 660514 g05d frequency (mhz) 0.1 phase (deg) group delay (ns) C60C90 C120 30 5550 45 40 35 30 25 20 15 10 5 0 C30 10 1 100 660514 g05i phase group delay 100mv/div 660514 g05j 20ns/div gain = 1v/ v downloaded from: http:///
ltc6605-14 14 660514f input impedancecalculating the low frequency input impedance depends on how the inputs are driven. figure 6 shows a simpli? ed low frequency equivalent cir- cuit. for balanced input sources (v inp = Cv inm ), the low frequency input impedance is given by the equation: r inp = r inm = r1 therefore, the differential input impedance is simply: r in(diff) = 2 ? r1 applications information C + r2 v out C v out + v ocm v outdiff 0.1 f 660514 f06 r1 r inp v inp v inm r1 r2 r3 r3 ++ C C + C r inm figure 6. input impedance for single-ended inputs (v inm = 0), the input impedance increases over the balanced differential case due to the fact that the summing node (at the junction of r1, r2 and r3) moves in phase with v inp to bootstrap the input impedance. referring to figure 6 with v inm = 0, the input impedance looking into either input is: r inp = r inm r1 1 1 2 ? r2 r1 + r 2
input common mode voltage range the input common mode voltage is de? ned as the average of the two inputs into resistor r1: v incm = v inp + v inm 2 the input common mode range is a function of the ? lter con? guration (gain), v indiff and the v ocm potential. referring to figure 6, the summing junction where r1, r2 and r3 merge together should not swing within 1.4v of the v + power supply. additionally, to avoid forward biasing the esd protection diodes on the input pins, neither input should swing further than 325mv below the v C power rail. therefore, the input common mode voltage should be constrained to: v 325mv + v indiff 2 v incm 1 + r1 r 2 ?v + 1.4v () r1 r 2 v ocm the speci? cations in the electrical characteristics table are a special case of the general equation above. for a single 3v power supply, (v + = 3v, v C = 0v) with v ocm = 1.5v, v indiff = 0.25v and r1 = r2, the valid input common mode range is: C200mv v incm 1.7v likewise, for a single 5v power supply, (v + = 5v, v C = 0v) with v ocm = 2.5v, v indiff = 0.25v and r1 = r2, the valid input common mode range is: C200mv v incm 4.7v output common mode and v ocm pin the output common mode voltage is de? ned as the aver- age of the two outputs: v outcm = v ocm = v out + + v out ? 2 as the equation shows, the output common mode voltage is independent of the input common mode voltage, and is instead determined by the voltage on the v ocm pin, by means of an internal feedback loop.if the v ocm pin is left open, an internal resistor divider develops a potential halfway between the v + and v C volt- ages. the v ocm pin can be overdriven to another voltage if desired. for example, when driving an adc, if the adc makes a reference available for setting the common mode voltage, it can be directly tied to the v ocm pin, as long as the adc is capable of driving the input impedance presented by the v ocm pin as listed in the electrical characteristics table (r vocm ). the electrical characteristics table also speci? es the valid range that can be applied to the v ocm pin. downloaded from: http:///
ltc6605-14 15 660514f applications information noise when comparing the ltc6605-14s noise to that of other ampli? ers, be sure to compare similar speci? - cations. standalone op amps often specify noise re- ferred to the inputs of the op amp. the ltc6605-14s internal op amp has input referred voltage noise of only 2.1nv/ hz . in addition to the noise generated by the ampli? er, the surrounding feedback resistors also contribute noise. a noise model is shown in figure 7a. the output spot noise generated by both the ampli? er and the feedback components is given in figure 7b. substituting the equation for johnson noise of a resistor (e 2 nr = 4ktr) into the equation in figure 7b and simplify- ing gives the result shown in figure 7c. figure 7a. differential noise model figure 7b figure 7c C + 660514 f07a r1 r1 r3 e ni 2 e no 2 e nr3 2 r3 e nr3 2 r2 e nr2 2 r2 e nr2 2 e nr1 2 e nr1 2 i n + 2 i n C 2 e no = e ni ?1 + r2 r 1
2 + 2? i n ?r2 + r3 ? 1 + r2 r 1

2 + 2? e nr1 ? r2 r 1
2 + 2? e nr3 ?1 + r2 r 1
2 + 2?e nr2 2 e no = e ni ?1 + r2 r 1
2 + 2? i n ?r2 + r3 ? 1 + r2 r 1

2 + 8?k?t? r2? 1 + r2 r 1 + r3 ? 1 + r2 r 1 2

downloaded from: http:///
ltc6605-14 16 660514f board layout and bypass capacitors for single-supply applications it is recommended that a high quality x5r or x7r, 0.1f bypass capacitor be placed directly between v + and the adjacent v C pin. the v C pins, including the exposed pad, should be tied directly to a low impedance ground plane with minimal routing. for split power supplies, it is recommended that addi- tional high quality x5r or x7r, 0.1f capacitors be used to bypass pin v + to ground and v C to ground, again with minimal routing. for driving heavy differential loads (< 200), additional bypass capacitance may be needed between v + and v C for optimal performance. keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self-resonant frequency than do leaded capacitors, and perform best in high speed applications. the v ocm pins should be bypassed to ground with a high quality ceramic capacitor (at least 0.01f). in split-sup- ply applications, the v ocm pin can be either bypassed to ground or directly hard wired to ground.stray parasitic capacitances to any unused input pins should be kept to a minimum to prevent deviations from the ideal frequency response. the best approach is to remove the solder pads for the unused component pins and strip applications information away any ground plane underneath. floating unused pins does not reduce the reliability of the part. at the output, always keep in mind the differential nature of the ltc6605-14, because it is important that the load impedances seen by both outputs (stray or intended) be as balanced and symmetric as possible. this will help pre- serve the balanced operation that minimizes the generation of even-order harmonics and maximizes the rejection of common mode signals and noise. driving adcs the ltc6605-14s rail-to-rail differential output and ad- justable output common mode voltage make it ideal for interfacing to differential input adcs. these adcs are typically supplied from a single-supply voltage which can be as low as 3v (2.7v minimum), and have an optimal com- mon mode input range near mid-supply. the ltc6605-14 makes interfacing to these adcs easy, by providing antialiasing, single-ended to differential conversion and common mode level shifting. the sampling process of adcs creates a transient that is caused by the switching in of the adc sampling capaci- tor. this momentarily shorts the output of the ampli? er as charge is transferred between ampli? er and sampling capacitor. the ampli? er must recover and settle from this downloaded from: http:///
ltc6605-14 17 660514f figure 8. driving an adc 660514 f08 3.3v 0.1f 2.2f 1f 1f bias = r ? (c1 + 2 ? c2) control adc 3v d15 ?? d0 v ocm v in C + 21 19 a in + a in C v cm gnd 22 18 10nf 2 3 4 1 5 20 c1 c2 rr c1 + C 1/2 ltc6605-14 channel a 10 10 applications information load transient before the acquisition period has ended, for a valid representation of the input signal. the ltc6605-14 will settle quickly from these periodic load impulses. the rc network between the outputs of the driver decouples the sampling transient of the adc (see figure 8). the capacitance serves to provide the bulk of the charge during the sampling process, while the two resistors at the outputs of the ltc6605-14 are used to dampen and attenuate any charge injected by the adc. the rc ? lter gives the add itional bene? t of band limiting broadband output noise. the selection of the rc time constant is trial and error for a given adc, but the following guidelines are recommended. choose an rc time constant that is smaller than the reciprocal of the ? lter cutoff frequency con? gured by the ltc6605-14. t ime constants on the order of 2ns do a good job of ? ltering broadband noise. longer time constants improve snr at the expense of settling time. the resistors in the decoupling network should be at least 25. too large of a resistor will leave insuf? cient settling time. too small of a resistor will not properly dampen the load transient of the sampling process, prolonging the time required for settling. in 16-bit applications, this will typically require a minimum of eleven rc time constants. the 10 resistors at the inputs to the adc minimize the sampling transients that charge the rc ? lter capacitors. for lowest distortion, choose capacitors with low dielectric absorption, such as a c0g multilayer ceramic capacitor. downloaded from: http:///
ltc6605-14 18 660514f typical applications dual, matched, 4th order 14mhz lowpass filter three gains are possible,as shown in figure 4 1.4k1.4k ltc6605-14 ltc6605-14 v ina v inb v outa v outb C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 660514 ta02 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 gain magnitude vs frequency frequency (mhz) 0.1 gain (db) 10 0 C10C20 C30 C40 C50 C60 1 10 100 660514 ta03 downloaded from: http:///
ltc6605-14 19 660514f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 0.10 (2 sides) note:1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package note: 1. dimensions are in millimeters 2. apply solder mask to areas that are not soldered 3. drawing is not to scale 0.40 0.05 pin #1 notchr0.30 typ or 0.25mm 45 chamfer bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.10 typ 1 22 1211 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (djc) dfn 0605 6.00 0.10 (2 sides) 0.25 0.05 0.889 0.889 0.50 bsc 5.35 0.10 (2 sides) r = 0.10 recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.70 0.05 3.60 0.05 packageoutline 0.25 0.05 0.50 bsc 5.35 0.05 (2 sides) 0.889 0.889 package description djc package 22-lead plastic dfn (6mm 3mm) (reference ltc dwg # 05-08-1714) downloaded from: http:///
ltc6605-14 20 660514f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 1208 printed in usa related parts typical application part number description comments lt1568 4th order filter building block lowpass and bandpass respo nses up to 10mhz ltc6404 rail-to-rail output differential op amp 1.5nv/ hz noise, C95dbc distortion at 10mhz ltc6406 3ghz rail-to-rail input differential op amp 1.6nv/ hz noise, C72dbc distortion at 50mhz, 18ma lt6600-2.5/lt6600-5/ lt6600-10/lt6600-15/ lt6600-20 differential 4th order lowpass filters cut-off frequencies of 2.5mhz/5mhz/10mhz/15mhz/20mhz ltc6601 differential pin-con? gurable 2nd order filter building block 7mhz to 25mhz pin-con? gurable lt6604-2.5/lt6604-5 dual differential 4th order lowpass filter s cut-off frequencies of 2.5mhz or 5mhz dual, matched, 2nd order 25mhz lowpass filter gain magnitude vs frequency ltc6605-14 v ina v inb v outa v outb 660514 ta04 C + 22 18 C + 16 12 2 4 1 5 8 10 7 11 frequency (mhz) 0.1 gain (db) 30 C3C6 C9 C12C15 C21 C18C24 1 10 100 660514 ta05 downloaded from: http:///

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